The present invention relates to a buffer memory subsystem for use in data processing systems and, more particularly, to a buffer memory subsystem that facilitates access of data stored in a buffer memory by a peripheral controller.
In the field of data processing, peripheral devices such as mass storage devices, printers, modems and the like often require certain control logic for proper operation. In earlier, simple systems, the central processing unit (CPU) controlled peripheral equipment operations directly. But as systems became more sophisticated, more peripheral devices were added to complex systems and the speed of data processing operations increased, it became evident that CPU's could not adequately control peripheral equipment and still be available for other duties, such as system control, interfacing and data manipulation.
In previous systems, a CPU was connected to one or more peripheral devices over a single data communications channel or bus. Throughput of the single data communications bus, however, was soon degraded when the CPU attempted to access or communicate with two or more devices.
As peripheral equipment became more efficient, each device could perform more activities faster, thus increasing overall data communications bus usage. This increase in bus communications resulted in increased risk of data bottleneck. Thus, more sophisticated arbitration mechanisms were required to control communications among the peripheral equipment devices and the CPU.
A great advance in efficiency in data processing systems occurred when controllers were developed to control peripheral devices intelligently so that CPU's could be freed for other operations. Each peripheral controller was provided to control individual peripheral devices on the bus. It is most efficient for a peripheral controller to control one or more devices of the same type (e.g., magnetic hard disks).
To increase the efficiency of systems further, two communications buses were then provided. In this way, a high speed, efficient data communications bus could be used for high speed communications between the peripheral controller and the peripheral devices. On the other hand, a slower, less efficient CPU data communications bus could be used between the CPU and the peripheral controller, since data communications between CPU and controller generally need not be handled at the same high rate of speed as are communications between controller and peripheral devices for overall system management.
The use of a dynamic memory as a buffer device connected to the communications bus between the peripheral devices and the peripheral controller was also proven to be very effective. The buffer memory allowed data from the peripheral device (e.g., disk) to be stored temporarily, pending correction, for instance. This could occur while data input to the system from a high speed data communications bus, such as a small computer system interface (SCSI), which is attached to a host processor, could be transmitted to the peripheral controller directly. In this way, communications between the peripheral device and the peripheral controller need not limit other, higher speed communications between the host processor and the rest of the peripheral subsystem.
The data communications bus disposed between peripheral controller and buffer memory is known as a buffer bus. Although the peripheral controller has access to the buffer bus in most cases, occasionally it is the CPU that requires access to devices located on the buffer bus. In those cases, when the CPU and the peripheral controller are in contention for the buffer bus, an arbitration mechanism is required.
Heretofore, an arbiter was provided between the buffer bus and the peripheral controller and CPU. This arbiter consisted of external logic, requiring separate transceivers for communications with the peripheral controller and with the CPU. Recently, a desire for fewer components taking less space on printed circuit boards has made arbiters of the foregoing description inappropriate.
It would be advantageous to provide an arbiter function without using external logic.
It would also be advantageous to provide an arbitration mechanism within a peripheral controller itself.
It would also be advantageous to allow a CPU to access a buffer bus when necessary without contending with a peripheral controller.
It would also be advantageous to permit a buffer memory subsystem to operate with two separate communication buses isolated from one another.
It would also be advantageous to provide an arbitration mechanism in a peripheral controller to arbitrate buffer bus access requests from a plurality of initiating devices.